VILLACH
BESTES MATCHBALDIGER BEWERBUNGSSCHLUSS
... Engineering , Computer Science or equivalent At least 5 years of experience in mixed signal IC design/layout/verification or support Programming skills : Python, Perl, Tcl, SKILL (Cadence ... tools like Cadence (Virtuoso, Spectre,Xcelium, AMS-Designer, Genus, Innovus), Synopsys (DC, ICC) and Siemens/Mentor (Calibre, Solido) Know-how in full custom layout design techniques ...
